Automated Test Case Generation for Chip Verification Using Deep Reinforcement Learning

Abstract

This paper presents a novel automated test case generation framework leveraging deep reinforcement learning (DRL) for chip verification. The framework addresses the growing complexity in modern chip designs where traditional verification methods must help achieve comprehensive coverage efficiently. Our approach implements a custom deep Q-network architecture optimized for processing coverage feedback and generating test vectors, incorporating an innovative reward mechanism that balances coverage optimization with simulation efficiency. The proposed system features a hierarchical state space representation scheme that captures temporal and spatial aspects of coverage progression, combined with an adaptive training strategy that dynamically adjusts to verification requirements. The framework is evaluated on multiple industrial-scale benchmark designs, demonstrating significant improvements over conventional methods, achieving up to 98.5% functional coverage with a 45% reduction in verification time. The distributed implementation demonstrates near-linear scaling across multiple GPU nodes while maintaining high resource utilization efficiency. Experimental results show that the DRL-based approach outperforms traditional constrained-random and coverage-driven test generation methods across various metrics, including coverage rate, corner case detection, and simulation efficiency. The framework's integration with existing verification workflows and its ability to handle complex design scenarios make it particularly suitable for modern chip verification challenges.